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ds05-20876-3e fujitsu semiconductor data sheet flash memory cmos 4 m (512 k 8) bit mbm29f004tc/004bc- 70/ - 90 n description the mbm29f004tc/bc is a 4 m-bit, 5.0 v-only flash memory organized as 512 k bytes of 8 bits each. the mbm29f004tc/bc is offered in a 32-pin tsop (1) and 32-pin qfj (plcc) packages. this device is designed to be programmed in-system with the standard system 5.0 v v cc supply. a 12.0 v v pp is not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard mbm29f004tc/bc offers access times between 70 ns and 90 ns allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ) , write enable (we ) , and output enable (oe ) controls. the mbm29f004tc/bc is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 v flash or eprom devices. (continued) n product line up part no. mbm29f004tc/bc -70 -90 ambient temperature ( c) - 20 to + 70 - 40 to + 85 max address access time (ns) 70 90 v cc supply voltage 5.0 v 10 % voltage consumption (mw) (max) operation 193 erase/program 275 ttl standby mode 5.5 cmos standby mode 0.0275 max ce access (ns) 70 90 max oe access (ns) 30 35
mbm29f004tc/004bc -70/90 2 (continued) the mbm29f004tc/bc is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. each sector can be programmed and verified in less than 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. any individual sector is typically erased and verified within 1.0 second (if already completely preprogrammed) . this device also features a sector erase architecture. the sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. the mbm29f004tc/bc is erased when shipped from the factory. the mbm29f004tc/bc device also features hardware sector group protection. this feature will disable both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. fujitsu has implemented an erase suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a non-busy sector. true background erase can thus be achieved. the device features single 5.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations during power transitions. the end of program or erase is detected by data polling of dq 7 , or by the toggle bit i feature on dq 6 output pin. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. fujitsu's flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29f004tc/bc memory electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection. n pac k ag e 32-pin plastic tsop (1) 32-pin plastic tsop (1) 32-pin plastic qfj (plcc) (fpt-32p-m24) (fpt-32p-m25) (lcc-32p-m02) marking side marking side
mbm29f004tc/004bc -70/90 3 n features ? single 5.0 v read , write , and erase minimizes system level power requirements ? compatible with jedec - standard commands pinout and software compatible with single-power supply flash superior inadvertent write protection ? 32-pin tsop (1) (package suffix : pftn-normal bend type, pftr-reverse bend type) 32-pin plcc (package suffix : pd) ? minimum 100,000 write/erase cycles ? high performance 70 ns maximum access time ? flexible sector erase architecture one 16 k byte, two 8 k bytes, one 32 k byte, and seven 64 k bytes sectors any combination of sectors can be erased. also supports full chip erase. ? embedded erase?* algorithms automatically pre-programs and erases the chip or any sector ? embedded program?* algorithms automatically programs and verifies data at specified address ? data polling and toggle bit feature for detection of program or erase cycle completion ? low v cc write inhibit 3.2 v ? erase suspend / resume supports reading or programming data to a sector not being erased ? sector protection hardware sector protect that disables any combination of sectors from write or erase operations ? temporary sector unprotection temporary sector unprotection via the command sequence ? boot code sector architecture ? fast programming ? extended sector protection *: embedded erase?, embedded program? and expressflash? are trademarks of advanced micro devices, inc.
mbm29f004tc/004bc -70/90 4 n pin assignments (continued) tsop (1) (marking side) (fpt-32p-m24) (marking side) (fpt-32p-m25) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a 10 ce dq 7 dq 6 dq 5 dq 4 dq 3 v ss dq 2 dq 1 dq 0 a 0 a 1 a 2 a 3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a 11 a 9 a 8 a 13 a 14 a 17 we v cc a 18 a 16 a 15 a 12 a 7 a 6 a 5 a 4 normal bend 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss dq 3 dq 4 dq 5 dq 6 dq 7 ce a 10 oe 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a 4 a 5 a 6 a 7 a 12 a 15 a 16 a 18 v cc we a 17 a 14 a 13 a 8 a 9 a 11 reverse bend
mbm29f004tc/004bc -70/90 5 (continued) n pin description table 1 mbm29f004tc/bc pin configuration pin function a 18 to a 0 address inputs dq 7 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable/sector protection unlock v ss device ground v cc device power supply (5.0 v 10 % ) 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 a 14 a 13 a 8 a 9 a 11 oe a 10 ce dq 7 a 12 a 15 a 16 a 18 v cc we a 17 dq 1 dq 2 v ss dq 3 dq 4 dq 5 dq 6 14 15 16 17 18 19 20 4 3 2 1 32 31 30 plcc (top view) (lcc-32p-m02)
mbm29f004tc/004bc -70/90 6 n block diagram n logic symbol v ss v cc we ce a 18 to a 0 oe dq 7 to dq 0 stb stb erase voltage generator state control command register program voltage generator input/output buffers data latch chip enable output enable logic low v cc detector timer for program/erase address latch y-decoder x-decoder y-gating cell matrix 4,194,304 19 a 18 to a 0 we oe ce dq 7 to dq 0 8
mbm29f004tc/004bc -70/90 7 n device bus operation table 2 mbm29f004tc/bc user bus operations legend : l = v il , h = v ih , x = h or l, = pulse input. see dc characteristics for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. refer to table 6. *2 : we can be v il if oe is v il , oe at v ih initiates the write operations. *3 : refer to the section on sector protection. *4 : to activate the command, oe has to be taken to v id . *5 : in case of command mode sector protect. *6 : in case of hardware sector protect. operation ce oe we a 0 a 1 a 6 a 9 i/o auto-select manufacturer code* 1 llhlllv id code auto-select device code* 1 llhhllv id code read* 2 llha 0 a 1 a 6 a 9 d out standby h x x x x x x high-z output disable l h h x x x x high-z write (program/erase) l h l a 0 a 1 a 6 a 9 d in enable sector protection* 3 lv id xxxv id x 3-byte sector unlock sequence l v id a 0 a 1 a 6 a 9 d in 2-byte sector relock sequence l v id a 0 a 1 a 6 a 9 d in command mode sector protect* 2 lv id a 0 a 1 a 6 a 9 d in verify sector protect* 2, * 5 llha 0 a 1 a 6 a 9 code hardware sector protect* 2 hv id lxxlv id x verify sector protection* 2, * 6 llhlhlv id code temporary sector unprotection* 3 lv id a 0 a 1 a 6 a 9 d in
mbm29f004tc/004bc -70/90 8 table 3 mbm29f004tc/bc command definitions *1: either of the two reset commands will reset the device to read mode. *2: to activate the command, oe has to be taken to v id . *3: valid only during temporary sector unprotection mode. *4: valid only during extended sector protection set-up mode. (continued) command sequence * 1, * 2, * 3 bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset * 1 1 xxxh f0h ?????????? read/reset byte * 1 3 555h aah 2aah 55h 555h f0h ra rd ???? auto-select manufacture code 3 555h aah 2aah 55h 555h f0h 00h 04h ???? auto-select device code 3 555h aah 2aah 55h 555h 90h 01h id ???? program 4 555h aah 2aah 55h 555h a0h pa pd ???? chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend erase can be suspended during sector erase with addr (h or l) , data (b0h) sector erase resume erase can be resumed after suspend with addr (h or l) , data (30h) set to fast mode 3 555h aah 2aah 55h 555h 20h ?????? temporary sector unprotection mode * 2 3 555h aah 2aah 55h 555h 20h ?????? reset from fast mode * 8 2 xxxh 90h xxxh 00h ???????? sector unlock * 9 3 555h aah 2aah 55h 555h 24h ?????? fast programming * 3 2 xxxh a0h pa pd ???????? sector relock * 2 2 xxxh 90h xxxh f0h or 00h ???????? sector protection set function by extended sector protection command * 2 3 555h aah 2aah 55h 555h 24h ?????? extended sector protection 3 xxxh 60h spa 60h spa 40h spa sd ????
mbm29f004tc/004bc -70/90 9 (continued) notes : address bits x = h or l for all address commands except for program address (pa) and sector address (sa) . bus operations are defined in table 2. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we or ce pulse. sa = address of the sector to be erased. the combination of a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 will uniquely select any sector. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we or ce pulse. id = device code. (see table 4 autoselect codes. ) spa = sector protection address. sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0) to be set. sd = data to verify the sector protection. the output at protected sector = 01h and the output at unprotected sector = 00h. command combinations not described in mbm29f004tc/bc command definitions table are illegal. table 4.1 mbm29f004tc/bc sector protection verify autoselect codes * : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. table 4.2 expanded autoselect code table type a 18 to a 13 a 6 a 1 a 0 code (hex) manufactures code x v il v il v il 04h device code mbm29f004tc x v il v il v ih 77h mbm29f004bc x v il v il v ih 7bh sector protection sector addresses v il v ih v il 01h* type code dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code04h00000100 device code mbm29f004tc77h01110111 mbm29f004bc7bh01111011 sector protection 01h00000001
mbm29f004tc/004bc -70/90 10 n flexible sector-erase architecture ? one 16 k byte, two 8 k bytes, one 32 k byte, and seven 64 k bytes sectors. ? individual-sector, multiple-sector, or bulk-erase capability. ? individual or multiple-sector protection is user definable. table 5 sector address tables (mbm29f004tc) table 6 sector address tables (mbm29f004bc) sector address a 18 a 17 a 16 a 15 a 14 a 13 address range sa0 0 0 0 x x x 00000h to 0ffffh sa1 0 0 1 x x x 10000h to 1ffffh sa2 0 1 0 x x x 20000h to 2ffffh sa3 0 1 1 x x x 30000h to 3ffffh sa4 1 0 0 x x x 40000h to 4ffffh sa5 1 0 1 x x x 50000h to 5ffffh sa6 1 1 0 x x x 60000h to 6ffffh sa7 1 1 1 0 x x 70000h to 77fffh sa8 1 1 1 1 0 0 78000h to 79fffh sa9 1 1 1 1 0 1 7a000h to 7bfffh sa10 1 1 1 1 1 x 7c000h to 7ffffh sector address a 18 a 17 a 16 a 15 a 14 a 13 address range sa0 0 0 0 0 0 x 00000h to 03fffh sa1 0 0 0 0 1 0 04000h to 05fffh sa2 0 0 0 0 1 1 06000h to 07fffh sa3 0 0 0 1 x x 08000h to 0ffffh sa4 0 0 1 x x x 10000h to 1ffffh sa5 0 1 0 x x x 20000h to 2ffffh sa6 0 1 1 x x x 30000h to 3ffffh sa7 1 0 0 x x x 40000h to 4ffffh sa8 1 0 1 x x 0 50000h to 5ffffh sa9 1 1 0 x x 1 60000h to 6ffffh sa10 1 1 1 x x x 70000h to 7ffffh
mbm29f004tc/004bc -70/90 11 mbm29f004tc top boot sector architecture mbm29f004bc bottom boot sector architecture sector sector size ( 8) address range sa0 64 k bytes 00000h to 0ffffh sa1 64 k bytes 10000h to 1ffffh sa2 64 k bytes 20000h to 2ffffh sa3 64 k bytes 30000h to 3ffffh sa4 64 k bytes 40000h to 4ffffh sa5 64 k bytes 50000h to 5ffffh sa6 64 k bytes 60000h to 6ffffh sa7 32 k bytes 70000h to 77fffh sa8 8 k bytes 78000h to 79fffh sa9 8 k bytes 7a000h to 7bfffh sa10 16 k bytes 7c000h to 7ffffh sector sector size ( 8) address range sa0 16 k bytes 00000h to 03fffh sa1 8 k bytes 04000h to 05fffh sa2 8 k bytes 06000h to 07fffh sa3 32 k bytes 08000h to 0ffffh sa4 64 k bytes 10000h to 1ffffh sa5 64 k bytes 20000h to 2ffffh sa6 64 k bytes 30000h to 3ffffh sa7 64 k bytes 40000h to 4ffffh sa8 64 k bytes 50000h to 5ffffh sa9 64 k bytes 60000h to 6ffffh sa10 64 k bytes 70000h to 7ffffh
mbm29f004tc/004bc -70/90 12 n functional description read mode the mbm29f004tc/bc has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc -t oe time) . standby mode when using ce pin, a cmos standby mode is achieved with ce input held at v cc 0.3 v. under this condition the current consumed is less than 5 m a. a ttl standby mode is achieved with ce pin held at v ih . under this condition the current is reduced to approximately 1 ma. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = v ih . the device can be read with standard access time (t ce ) from either of these standby modes. in this mode, all outputs pins are placed in the high impedance state. output disable with the oe input at a logic high level (v ih ) , output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 . (see table 4.1 and 4.2.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29f004tc/bc is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 3. (refer to autoselect command section.) byte 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and byte 1 (a 0 = v ih ) represents the device identifier code for mbm29f004tc = 77h, mbm29f004bc = 7bh. these two bytes are given in the tables 4.1 and 4.2. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see tables 4.1 and 4.2.) the autoselect mode also facilitates the determination of sector group protection in the system. by performing a read operation at the address location xx02h with the higher order address bit a 13 , a 14 , a 15 , a 16 , a 17 and a 18 set to the desired sector address, the device will return 01h for a protected sector group and 00h for a non- protected sector. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters.
mbm29f004tc/004bc -70/90 13 sector group protection the mbm29f004tc/bc features hardware sector group protection. these features will disable both program and erase operations in any combination of sectors (0 through 10) . the sector group protection feature is enabled using programming equipment at the users site. the device is shipped with all sector group unprotected. to activate command mode sector group protection, the programming groups equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 12 v) , ce = v il , a6 = v il . the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) should be set to the sector to be protected. tables 5 and 6 define the sector address for each of the eleven (11) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 12 and 20 for sector protection waveforms and algorithm. to verify programming of the command mode sector protection circuitry, the programming equipment must force v id on address a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) while (a 6 , a 5 , a 1 , a 0 ) = (0, 1, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , a 5 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. the alternate hardware sector protect mode intended only for the programming equipment required force v id on address pin a 9 and control pin oe , (suggest v id = 12 v) , ce = v il . the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) should be set to the sector to be protected. tables 4 and 5 define the sector address for each of the eleven (11) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 15 and 23 for sector protection waveforms and algorithm. to verify programming of the hardware sector protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) are the desired sector group address will produce a logical 1 at dq 0 for a protected sector group. see tables 3.1 and 3.2 for autoselect codes. temporary sector unprotection this feature allows temporary unprotect of previously protected sector of the mbm29f004tc/bc device in order to change data. the temporary sector unprotection mode is activated by setting the oe pin to high voltage (12 v) . while oe is at v id , the sector unlock sequence is written to the device. after the sector unlock sequence is written, the oe pin is taken back to v ih . the device is now in the temporary sector unprotection mode. while in this mode, formerly protected sectors can be programmed or erased by selecting the appropriate sector addresses during programming or erase operations. either sector erase or chip erase operations can be per- formed in this mode. exiting the temporary sector unprotection mode is accomplished by either removing v cc from the device or by taking oe back to v id and writing the sector relock sequence. after writing the sector relock sequence, the oe pin is taken back to v ih and all previously protected sectors will be protected again. the temporary sector unprotection status can be used to check whether this mode is in operation or not. the temporary sector unprotection status can be executed by setting a o = a i = v ih (a 6 = v il ) during autoselect mode.
mbm29f004tc/004bc -70/90 14 n command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to read mode. table 3 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both read/ reset commands are functionally equivalent, resetting the device to the read mode. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory at the read/reset operation. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read character- istics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h returns the device code (mbm29f004tc = 77h, mbm29f004bc = 7bh) . (see tables 4.1 and 4.2) all manufacturer and device codes will exhibit odd parity with the msb (dq 7 ) defined as the parity bit. sector state (protect or unprotect) will be informed by address xx02h. scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. to terminate the operation, it is necessary to write the read/reset command sequence into the register and also to write the autoselect command during the operation, execute it after writing read/reset command se- quence. byte programming the device is programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. (see table 6, hardware sequence flags.) therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if a hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written.
mbm29f004tc/004bc -70/90 15 programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 16 illustrates the embedded programming tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section) at which time the device returns to read the mode. figure 17 illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we (whichever happens first) , while the command (data = 30h) is latched on the rising edge of ce or we (whichever happens first) . after time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command (30h) to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 m s otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last ce or we will initiate the execution of the sector erase command (s) . if another falling edge of the ce or we occurs within the 50 m s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, write operation status section for dq 3 , sector erase timer operation.) resetting the device once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 6) . sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 m s time out from the rising edge of the ce or we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. figure 17 illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during a sector erase operation which includes the time-out period for sector erase and will be ignored during chip erase or programming
mbm29f004tc/004bc -70/90 16 operations. writing the erase suspend command during the sector erase time-out results in immediate termi- nation of the time-out period and suspension of the erase operation. any other command written during the erase suspend mode will be ignored except the erase resume command. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 15 m s to suspend the erase operation. when the device has entered the erase-suspended mode, the dq 7 bit will be at logic 1 and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular byte program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the data polling of dq 7 , or by the toggle bit i (dq 6 ) which is the same as the regular byte program operation. note that dq 7 must be read from the byte program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode mbm29f004tc/bc has fast mode function. this feature allows the system to program the device faster than using the standard program command sequence. the fast mode command sequence is initiated by setting the oe pin to v id and writing two unlock cycles. this is followed by a third write cycle containing the fast mode command, 20h. the device then enters the fast mode. previously protected sectors of the device are now temporarily unprotected. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standerd program command sequence, resulting in faster total programming time. tables 6 and 7 show the requirements for the command sequence. during the unlock bypass mode, only the fast program and reset from fast mode commands are valid. to exit the fast mode, the system must issue the two-cycle unlock bypass reset command sequence with oe at v id . the first cycle must contain the data 90h; the second cycle the data 00h. addresses are dont care for both cycles. the device then returns to reading array data. (refer to the figure 24 extended algorithm.) (2) fast programming during temporary sector unprotection mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd) . sector relock to relock temporary sector unprotection or extended sector protection, oe pin should be forced to v 2h after relock sector command sequence with oe pin, that is forced v id .
mbm29f004tc/004bc -70/90 17 extended sector protection set-up this function operation is for the execution of extended sector protection. this mode is excuted by forcing v ih on oe pin after a command sequences with oe pin, that is forced v id . extended sector protection/extended sector protection set-up in this mode, the operation is initiated by writing the set-up command (60h) into the command register after extended sector protection set-up command. then, the sector addresses pin (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins) , and write extended sector protection command (60h) . a sector is typically protected in 100 m s. to verify programming of the protection circuitry, the sector addresses pins (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h) . following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector protection command (60h) again. to terminate the operation it is necessary relock the sector. this command is the same function as the sector protection. write operation status detailed in table 8 are all the status flags that can be used to check the status of the device for current mode operation. during sector erase, the part provides the status flags automatically to the i/o ports. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consecutively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows the user to determine which sectors are erasing and which are not. once erase suspend is entered, address sensitivity still applies. if the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. if the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. table 6 hardware sequence flags *1 : performing successive read operations from any address will cause dq 6 to toggle. *2 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. notes : dq 0 and dq 1 are reserve pins for future use. dq 4 is fujitsu internal use only. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle erase suspend- ed mode erase suspend read (erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle* 1 001* 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspend- ed mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29f004tc/004bc -70/90 18 dq 7 data polling the mbm29f004tc/bc device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . the data polling is valid after the rising edge of the forth write pulse sequence. during the embedded erase tm algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in figure 18. data polling will also flag the entry into erase suspend. dq 7 will switch 0 to 1 at the start of the erase suspend mode. please note that the address of an erasing sector must be applied in order to observe dq 7 in the erase suspend mode. during program in erase suspend, data polling will perform the same as in regular program execution outside of the suspend mode. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth we pluse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being pro- grammed or erased. otherwise, the status may not be valid and data polling at a protected sector may not be correctly performed. in this case, the toggle bit i will be recommended. just prior to the completion of embedded algorithm operation, mbm29f004tc/bc data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operations and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algo- rithm, erase suspend, or sector erase time-out. see figure 9 for the data polling timing specifications and waveforms. dq 6 toggle bit i the mbm29f004tc/tb also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulse sequence. the toggle bit i is active during the sector erase time out. in programming, if the sector being written to is protected, the toggle bit i will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit i for about 100 m s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. see figure 10 for the toggle bit i timing specifications and diagrams.
mbm29f004tc/004bc -70/90 19 dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . under these conditions dq 5 will produce a 1. this is a failure condition which indicaters that the program or erase cycle was not successfully completed. data polling dq 7 , dq 6 is only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma) . the oe and we pins will control the output disable functions as described in table 2. the dq 5 failure condition may also appear if a user tries to program a 1 to a location that is previously programmed to 0. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. dq 3 will remain low until the time-out is completed. data polling and toggle bit i are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) , the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0) the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. refer to table 6 : hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase tm algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase tm algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. for example, dq 2 and dq 6 can be used together to determine the erase-suspend-read mode (dq 2 toggles while dq 6 does not) . see also table 6 and figure 14. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from the erasing sector. table 9 toggle bit status *1 : these status flags apply when outputs are read from a sector that has been erase-suspended. *2 : these status flags apply when outputs are read from the byte address of the non-erase suspended sector. mode dq 7 dq 6 dq 2 program dq 7 toggles 1 erase 0 toggles toggles erase-suspend read* 1 (erase-suspended sector) 1 1 toggles erase-suspend program dq 7 * 2 toggles 1* 2
mbm29f004tc/004bc -70/90 20 data protection the mbm29f004tc/bc is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completions of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 3.2 v (typically 3.7 v) . if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 3.2 v. the embedded program algorithm will be stopped under the v cc level is less than v lko . the embedded program algorithm will not be restart even if the v cc level satisfy the recommended v cc supply voltage again. then, if the embedded program algorithm is stopped during the program ro erase operation is in progress, the address data is not correct and the programming or erase command should be written again. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up. sector unprotection mbm29f004tc/bc features hardware sector protection at users side. this feature will disable both program and erase operations in protected sectors. the programming and erase command to the protected sector will be ignored.
mbm29f004tc/004bc -70/90 21 n absolute maximum ratings *1 : voltage : gnd = 0 v *2 : minimum dc voltage on input and l/o pins are - 0.5 v. during voltage transitions, inputs may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input and i/o pins are v cc + 0.5 v. during voltage transitions, inputs may overshoot to v cc + 2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on a 9 and oe pins are - 0.5 v. during voltage transitions, a 9 , oe pins are + 13.0 v which may overshoot to 14.0 v for periods of up to 20 ns. voltage difference between input voltage and power supply. (v in - v cc ) do not exceed 9 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating ranges note : operating ranges define those limits between which the proper device function is quaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 40 + 85 c voltage with respect to ground all pins except a 9 and oe * 1, * 2 v in , v out - 2.0 + 7.0 v v cc * 1, * 2 v cc - 2.0 + 7.0 v a 9 and oe * 1, * 3 v in - 2.0 + 13.5 v parameter symbol part no. value unit min typ max ambient temperature t a mbm29f004tc/bc-70 - 20 ?+ 70 c mbm29f004tc/bc-90 - 40 ?+ 85 c v cc supply voltage v cc mbm29f004tc/bc-70/-90 + 4.5 5.0 + 5.5 v gnd 0
mbm29f004tc/004bc -70/90 22 n maximum overshoot/maximum undershoot + 0.8 v - 0.5 v 20 ns - 2.0 v 20 ns 20 ns figure 1 maximum undershoot waveform v cc + 0.5 v + 2.0 v v cc + 2.0 v 20 ns 20 ns 20 ns figure 2 maximum overshoot waveform 1 + 13.0 v v cc + 0.5 v + 13.5 v 20 ns 20 ns 20 ns figure 3 maximum overshoot waveform 2 note : this waveform is applied for a 9 and oe .
mbm29f004tc/004bc -70/90 23 n dc characteristics *1 : the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz) . the frequency component typically is 2 ma/mhz, with oe at v ih . *2 : i cc active while embedded algorithm (program or erase) is in progress. *3 : applicable to sector protection function. *4 : (v id - v cc ) do not exceed 9.0 v. parameter symbol conditions value unit min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max - 1.0 ? + 1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max - 1.0 ? + 1.0 m a a 9 , oe inputs leakage current i lit v cc = v cc max, a 9 , oe = 12.5 v ?? + 50 m a v cc active current* 1 i cc1 ce = v il , oe = v ih ?? 35 ma v cc active current* 2 i cc2 ce = v il , oe = v ih ?? 50 ma v cc current (standby) i cc3 v cc = v cc max, ce = v ih ?? 1ma v cc = v cc max, ce = v cc 0.3 v ? 15 m a input low level v il ?- 0.5 ? 0.8 v input high level v ih ? 2.0 ? v cc + 0.5 v voltage for autoselect and sector protection (a 9 , oe ) * 3, * 4 v id ? 11.5 12 12.5 v output low voltage level v ol i ol = 5.8 ma, v cc = v cc min ?? 0.45 v output high voltage level v oh1 i oh = - 2.5 ma, v cc = v cc min 2.4 ?? v v oh2 i oh = - 100 m av cc - 0.4 ?? v low v cc lock-out voltage v lko ? 3.2 3.7 4.2 v
mbm29f004tc/004bc -70/90 24 n ac characteristics ? read only operations characteristics parameter symbol test setup value (note) unit -70 -90 jedec standard min max min max read cycle time t avav t rc ? 70 ? 90 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 70 ? 90 ns chip enable to output delay t elqv t ce oe = v il ? 70 ? 90 ns output enable to output delay t glqv t oe ?? 30 ? 35 ns chip enable to output high-z t ehqz t df ?? 20 ? 20 ns output enable to output high-z t ghqz t df ?? 20 ? 20 ns output hold time from address, ce or oe , whichever occurs first t axqx t oh ? 0 ? 0 ? ns note : test conditions : output load : 1 ttl gate and 100 pf input rise and fall times : 5 ns input pulse levels : 0.45 v or 2.4 v timing measurement reference level input : 0.8 v and 2.0 v output : 0.8 v and 2.0 v c l 5.0 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w figure 4 test conditions note : c l = 100 pf including jig capacitance
mbm29f004tc/004bc -70/90 25 ? write / erase / program operations *1: this does not include the preprogramming time. *2: this timing is only for sector protection operation. parameter symbol value (note) unit -70 -90 jedec standard min typ max min typ max write cycle time t avav t wc 70 ?? 90 ?? ns address setup time t avwl t as 0 ?? 0 ?? ns address hold time t wlax t ah 45 ?? 45 ?? ns data setup time t dvwh t ds 30 ?? 45 ?? ns data hold time t whdx t dh 0 ?? 0 ?? ns output enable setup time ? t oes 0 ?? 0 ?? ns output enable hold time read ? t oeh 0 ?? 0 ?? ns toggle bit i and data polling 10 ?? 10 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? ns read recover time before write t ghel t ghel 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? ns write pulse width t wlwh t wp 35 ?? 45 ?? ns ce pulse width t eleh t cp 35 ?? 45 ?? ns write pulse width high t whwl t wph 20 ?? 20 ?? ns ce pulse width high t ehel t cph 20 ?? 20 ?? ns byte programming operation t whwh1 t whwh1 ? 8 ?? 8 ?m s sector erase operation * 1 t whwh2 t whwh2 ? 1 ?? 1 ? s ?? 8 ?? 8s v cc setup time ? t vcs 50 ?? 50 ??m s voltage transition time * 2 ? t vlht 4 ?? 4 ??m s write pulse width * 2 ? t wpp 100 ?? 100 ??m s oe setup time to we active * 2 ? t oesp 4 ?? 4 ??m s ce setup time to we active * 2 ? t csp 4 ?? 4 ??m s v id rise and fall time ? t vidr 500 ?? 500 ?? ns delay time from embedded output enable ? t eoe 30 ?? 35 ?? ns
mbm29f004tc/004bc -70/90 26 n erase and programming performance n pin capacitance 1.tsop (1) note : test conditions t a = 25 c, f = 1.0 mhz 2.qfj note : test conditions t a = 25 c, f = 1.0 mhz parameter limits unit comments min typ max sector erase time ? 18s excludes programming time prior to erasure byte programming time ? 8150 m s excludes system-level overhead chip programming time ? 4.2 10 s excludes system-level overhead program/erase cycle 100,000 ?? cycle ? parameter symbol test setup value unit typ max input capacitance c in v in = 078pf output capacitance c out v out = 0810pf control pin capacitance c in2 v in = 08.510pf parameter symbol test setup value unit typ max input capacitance c in v in = 078pf output capacitance c out v out = 0810pf control pin capacitance c in2 v in = 08.510pf
mbm29f004tc/004bc -70/90 27 n timing diagram ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l": any change permitted does not apply will be steady will be change from h to l will be change from l to h changing, state unknown center line is high- impedance "off" state a 18 to a 0 address stable high-z high-z ce oe we dq 7 to dq 0 output valid t rc t acc t oe t df t ce t oh t oeh figure 5.1 ac waveforms for read operation
mbm29f004tc/004bc -70/90 28 t acc t rc a 18 to a 0 dq 7 to dq 0 t oh output valid address stable high-z figure 5.2 ac waveforms for read operation
mbm29f004tc/004bc -70/90 29 a 18 to a 0 data ce oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t oh t oe t cs t ch notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. figure 6 ac waveforms for alternate we controlled program operation
mbm29f004tc/004bc -70/90 30 a 18 to a 0 data we oe ce 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh figure 7 ac waveforms for alternate ce controlled program operation notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. this command requires sector protection set-up.
mbm29f004tc/004bc -70/90 31 a 18 to a 0 data v cc ce oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h 30h for sector erase figure 8 ac waveforms for chip/sector erase operation * : sa is the sector address for sector erase. addresses = 555h (word) for chip erase.
mbm29f004tc/004bc -70/90 32 figure 9 ac waveforms for data polling during embedded algorithm operation * : dq 7 = valid data (the device has completed the embedded operation) . t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 2 = valid data dq 6 to dq 0 = output flag output valid oe we high-z high-z data data *
mbm29f004tc/004bc -70/90 33 t oeh ce we oe dq 6 t oe t oes data dq 6 =toggle dq 6 = stoptoggle output valid dq 6 =toggle note : dq 6 : stop toggling (the device completes the automatic operation.) figure 10 ac waveforms for toggle bit
mbm29f004tc/004bc -70/90 34 a 18 , a 17 , a 16 , a 15 , a 14 , a 13 a 0 a 1 a 6 a 9 v id 5 v oe v id 5 v we ce t oe t vlht t vlht t oesp t vlht t wpp t vlht data v cc sa x sa y t vcs t csp 01h figure 11 ac waveforms sector protection spax : sector address to be protected spay : next sector address to be protected note : a- 1 is v il on byte mode.
mbm29f004tc/004bc -70/90 35 oe ce address v ss v ih v id t vidr we 555h 2aah 555h data aah temporary sector unprotect mode disabled. read/reset mode enabled. temporary sector unprotect mode enabled or command mode sector protect enabled 55h 24h figure 11 3-byte sector unlock sequence timing diagram notes : to enable temporary sector unprotection mode, write 20h in data; to enable command mode sector protect, write 24h in data. to enable temporary sector unprotection mode, oe must be at v ih ; to enter command mode sector protect, oe must be held at v id . oe ce address v ss v ih v id t vidr we xxxh xxxh data 90h temporary sector unprotect mode enabled temporary sector unprotect mode disabled. read/reset mode enabled. f0h or 00h figure 12 2-byte sector relock sequence timing diagram
mbm29f004tc/004bc -70/90 36 oe ce address v ss v ih v id t vidr time-out: 100 m s for program t vlht we valid valid valid sector data 3-byte sector unlock sequence 2-byte sector relock sequence 60h 60h 40h valid figure 13 ac waveforms for command mode sector protect timing diagram notes : to enable the command mode sector protect, write 24h in data in 3-byte unlock sequence. for sector protect, a 6 = 0, a 5 = 1, a 1 = 1, a 0 = 0.
mbm29f004tc/004bc -70/90 37 oe ce a 18 to a 0 d 7 to d 0 v cc v id 5 v t vcs t vidr we t vlht 555h aah 55h 20h/24h 2aah 555h figure 12 ac waveforms for temporary sector unprotection/extended sector-protection set-up note : to execute temporary sector unprotection mode, 20h should be written. to execute extended sector protection mode, 24h should be written.
mbm29f004tc/004bc -70/90 38 a 0 add a 1 a 6 t vlht t oe time-out ce we data oe v id 5 v xxxh sa x sa x sa y 60h 01h 40h 60h 60h figure 13 ac waveforms for extended sector protection spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 100 m s (min) note : this command requires sector protection set-up
mbm29f004tc/004bc -70/90 39 figure 14 dq 2 vs. dq 6 note : dq 2 is read from the erase-suspended sector. enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 we toggle dq 2 and dq 6 with oe t vlht t vidr xxxh xxxh 90h oe ce a 18 to a 0 d 7 to d 0 v id 5 v we f0h or 00h note : this command is to complete temporary sector unprotection mode or extended sector protection. figure 15 ac waveforms for sector relock
mbm29f004tc/004bc -70/90 40 n flow chart figure 16 embedded program tm algorithm embedded algorithm 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in progress
mbm29f004tc/004bc -70/90 41 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional. figure 17 embedded erase tm algorithm embedded algorithm
mbm29f004tc/004bc -70/90 42 * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . note: va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector group addresses within the sector not being protected during sector erase or multiple sector erases operation. dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes figure 18 data polling algorithm
mbm29f004tc/004bc -70/90 43 figure 19 toggle bit algorithm *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. dq 6 = toggle? dq 5 = 1? read dq 7 to dq 0 addr. = "h" or "l" read dq 7 to dq 0 addr. = "h" or "l" read dq 7 to dq 0 addr. = "h" or "l" start no no yes yes *1 *1, 2 dq 6 = toggle? no yes program/erase operation not complete.write reset command program/erase operation complete read dq 7 to dq 0 addr. = "h" or "l"
mbm29f004tc/004bc -70/90 44 start no no no yes yes yes data = 01h? fail plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector group protection completed protect another sector group? plscnt = plscnt + 1 read from sector group addr. = sa, a 1 = v ih , a 6 , a 0 = v il setup sector group addr. (a 18 , a 17 ,a 16 , a 15 , a 14 , a 13 ) oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = ce = v il activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () * figure 20 sector group protection algorithm
mbm29f004tc/004bc -70/90 45 oe = v id oe = v ih oe = v id 555h/aah h/90h h/f0h or 00h 2aah/55h 555h/20h start temporary sector unprotect command sequence write temporary sector unprotect command sequence write temporary sector unprotect command sequence (address/command) temporary sector unprotect relock command sequence (address/command) temporary sector unprotection completed oe = v ih *1 perform erase or program operations *2 figure 21 temporary sector unprotection algorithm *1 : all protected sectors are unprotected. *2 : all previously protected sectors are protected once again.
mbm29f004tc/004bc -70/90 46 fail plscnt = 25? yes yes yes no no plscnt = 1 oe = v il data = 01h ? protect other sector ? oe = v id start wait to 4 m s plscnt = plscnt + 1 no yes oe = v ih setup sector protection write h/60h extended sector protection entry? device is operating in temporary sector unprotection mode no verify sector protection write 40h to sector address spa/40h a 1 = v ih , addr = sa, a 6 , a 0 = v il ( ) read from sector address a 1 = v ih , addr = sa, a 6 , a 0 = v il ( ) ( ) protect sector write spa/60h addr = sa, a 1 = v il , a 1 = v ih , a 6 = v il oe = v id oe = v ih oe = v id oe = v ih sector protection completed 555h/aah h/90h h/f0h or 00h 2aah/55h 555h/24h extended sector protection setup command (address/command) temporary sector unprotection relock command (address/command) write temporary sector unprotection unprotection command sequence write temporary sector unprotection unprotection command sequence extended sector protection set up command sequence write setup next sector address oe = v il figure 22 extended sector protection algorithm
mbm29f004tc/004bc -70/90 47 555h/aah oe = v id 555h/20h xxxxh/90h xxxxh/00h xxxh/a0h 2aah/55h program address/program data programming completed last address? increment address verify byte? data polling device start no no yes yes fast program completed set fast mode in fast program reset fast mode oe = v ih oe = v id oe = v ih figure 24 embedded program tm algorithm for fast mode fast mode algorithm
mbm29f004tc/004bc -70/90 48 n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of : mbm29f004 device number/description mbm29f004 4 mega-bit (512 k 8-bit) cmos flash memory 5.0 v read, write, and erase package type pd = 32-pin rectangular plastic leaded chip carrier (plcc) pftn = 32-pin thin small outline package (tsop) normal bend pftr = 32-pin thin small outline package (tsop) reverse bend speed option see product selector guide boot code sector architecture t = top sector b = bottom sector valid combinations mbm29f004tc-70 mbm29f004tc-90 pftn pftr pd mbm29f004bc-70 mbm29f004bc-90 valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local fujitsu sales office to confirm availability of specific valid combi- nations and to check on newly released combinations. tc -90 pd
mbm29f004tc/004bc -70/90 49 part no. package access (ns) mbm29f004tc-70pftn mbm29f004tc-90pftn 32-pin plastic tsop (1) (fpt-32p-m24) (normal bend) 70 90 top sector mbm29f004tc-70pftr mbm29f004tc-90pftr 32-pin plastic tsop (1) (fpt-32p-m25) (reverse bend) 70 90 mbm29f004tc-70pd mbm29f004tc-90pd 32-pin plastic qfj (plcc) (lcc-32p-m02) 70 90 MBM29F004BC-70PFTN mbm29f004bc-90pftn 32-pin plastic tsop (1) (fpt-32p-m24) (normal bend) 70 90 bottom sector mbm29f004bc-70pftr mbm29f004bc-90pftr 32-pin plastic tsop (1) (fpt-32p-m25) (reverse bend) 70 90 mbm29f004bc-70pd mbm29f004bc-90pd 32-pin plastic qfj (plcc) (lcc-32p-m02) 70 90
mbm29f004tc/004bc -70/90 50 n package dimensions (continued) 32-pin plastic tsop (1) (fpt-32p-m24) dimensions in mm (inches) C .003 +.001 .007 C 0.08 +0.03 0.17 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part "a" 0.10(.004) (mounting height) 1.10 +0.10 C 0.05 +.004 C .002 .043 (stand off) 0.10 0.05(.004 .002) (.315 .008) *8.00 0.20 0.10(.004) m (.009 .002) 0.22 0.05 (.724 .008) *18.40 0.20 (.787 .008) 20.00 0.20 lead no. index 17 16 32 1 2002 fujitsu limited f32035s-c-4-4 c 0.50(.020) note 1) * : resn protrusion. (each side : +0.15 (.006) max). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
mbm29f004tc/004bc -70/90 51 (continued) (continued) 32-pin plastic tsop (1) (fpt-32p-m25) dimensions in mm (inches) C .003 +.001 C 0.08 +0.03 .007 0.17 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part "a" 0.10(.004) (mounting height) index 1.10 +0.10 C 0.05 +.004 C .002 .043 (stand off) 0.10 0.05(.004 .002) 0.10(.004) m (.009 .002) 0.22 0.05 (.315 .008) *8.00 0.20 (.724 .008) *18.40 0.20 (.787 .008) 20.00 0.20 lead no. 17 16 32 1 2002 fujitsu limited f32036s-c-4-5 c 0.50(.020) note 1) * : resn protrusion. (each side : +0.15 (.006) max). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
mbm29f004tc/004bc -70/90 52 (continued) 32-pin plastic qfj (plcc) (lcc-32p-m02) dimensions in mm (inches) c 1994 fujitsu limited c32021s-2c-4 1 4 32 30 5 13 21 29 20 14 11.43?.08 (.450?003) 12.37?.13 (.487?005) 13.97?.08 (.550?003) 14.94?.13 (.588?005) 0.64(.025) min 2.25?.38 (.089?015) 3.40?.16 (.134?006) 12.95?.51 (.510?020) r0.95(.037) typ 1.27?.13 (.050?005) 7.62(.300)ref 10.16(.400) ref 0.43(.017) typ 0.66(.026) typ 10.41?.51 (.410?020) .008 ?001 +.002 ?.02 +0.05 0.20 0.10(.004) index no : lead no.
mbm29f004tc/004bc -70/90 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0303 ? fujitsu limited printed in japan

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